1. Field of the Invention
The present invention relates to a signal processing apparatus such as an FM multiplex data processing apparatus used in a VICS (Vehicle Information and Communication System) FM multiplex broadcast receiver and the like, and a semiconductor integrated circuit device incorporated into the signal processing apparatus, and in particular, to a clock noise reducing technique used in a semiconductor integrated circuit device such as an LSI analog filter circuit.
2. Description of the Related Art
FIG. 6 is a diagram showing a configuration of a conventional FM multiplex broadcast receiver for decoding VICS-FM multiplex data. An FM multiplex data processing apparatus 31 shown in FIG. 6 includes an analog filter IC 34, a VICS logic IC 35, and a microcontroller 36. The analog filter IC 34 extracts a VICS digital signal BPFO from an FM baseband signal (FM multiplex signal) containing multiplex data received through an FM antenna 2 and an FM tuner 3. The VICS logic IC 35 receives and decodes the digital signal BPFO output from the analog filter IC 34. The microcontroller 36 takes out and processes VICS data output from the VICS logic IC 35. The VICS-FM multiplex broadcast receiver is disclosed, for example, in Japanese Patent Kokai (Laid-open) Publication No. 11-234153.
FIG. 7 is a diagram showing a configuration of the analog filter IC 34 shown in FIG. 6. As shown in FIG. 7, the analog filter IC 34 includes a semiconductor integrated circuit component (IC chip) 40, a plurality of lead terminals (for inputting or outputting the signals BPFCLK, AIN, SG, and BPFO), and bonding wire terminals 41a, 43a, 44a, and 52a for connecting the lead terminals and electrode pads 41, 43, 44, and 52 of the IC chip 40. The electrode pad 41 of the analog filter IC 34 is supplied with a single-phase clock of 2 MHz, for instance, from the VICS logic IC 35. The IC chip 40 includes a variety of integrated circuit blocks formed on a semiconductor substrate, such as a low-pass filter (LPF) 43, an amplifier circuit (Amp) 46, a band-pass filter (BPF) 47 including a switched capacitor (SC) filter, an amplifier circuit (Amp) 48, a delay detection circuit (1/T) 49, a low-pass filter (LPF) 50, and an amplifier circuit (Amp) 51. The low-pass filter 43, the amplifier circuit 46, the band-pass filter 47, and the amplifier circuit 48 function as a filter block for extracting a digital signal of 76 kHz±4 kHz modulated by level-controlled minimum shift keying (LMSK) from the FM multiplex signal AIN, for instance. The delay detection circuit 49, the low-pass filter 50, and the amplifier circuit 51 function as a delay detection block for reproducing a 16 kbit/s digital signal BPFO from the LMSK-modulated digital signal, for instance.
In the analog filter IC 34 to which the single-phase clock BPFCLK is supplied from the VICS logic IC 35, however, parasitic capacitances Cp1, Cp2, Cp3, and Cp4, shown in FIG. 8, between the electrode pad 41 of the IC chip 40 and the integrated circuit blocks 45, 47, 49, and 50 respectively cause noise, which adversely affects the operating characteristics of the low-pass filters 45 and 50 and the band-pass filter 47. The effect of noise on the circuit characteristics is very large in a circuit having a capacitor which can temporarily float and has a relatively small capacitance. Incidentally, reduction of the effect of a noise signal is disclosed, for example, in Japanese Patent Kokai (Laid-open) Publication No. 2001-125744, and measures against stray capacitance are disclosed, for example, in Japanese Patent Kokai (Laid-open) Publication No. 2000-269793.